1. Field of the Invention
This disclosure relates to processors and, more particularly, to implementation of data prefetch systems.
2. Description of the Related Art
To improve execution performance, a processor may include one or more levels of cache memories (commonly referred to as “caches”). A cache may be used to store frequently accessed instructions and/or memory data, and improve performance by reducing the time for the processor to retrieve these instructions and data. A processor may include a fast low/first-level (L1) cache backed by a larger, slower second-level (L2) cache. Some processors may include a high/third-level (L3) cache for further performance improvement.
Some processors may include a prefetch buffer for a given cache to further improve memory access times. A prefetch buffer for the given cache may read data from a higher level cache or a system memory in anticipation of an upcoming request from the cache, i.e., prefetch data before the processor requests the data. A prefetch buffer may learn memory access patterns corresponding to one of more software processes running in the processor. Using these patterns, the prefetch buffer may then read data before the cache request it.
Prefetch buffers may have a fixed limit in terms of how many bytes of data may be prefetched (i.e., the look-ahead distance). For some software processes, the fixed limit may be too small, such that the data is read into the processor faster than the prefetch buffer can read it, which may result in the processor pausing execution to wait for the data. For other processes, if the fixed limit is too large, older data in the cache may be discarded to make room for the new data being fetched, which may result in data in active use by the processor being deleted too early or the prefetched data being stale (i.e., the original data is modified by another process or functional block in the system after being fetched).
Determining a look-ahead distance that adequately supports processes that consume data rapidly and processes that consume data slowly may be a difficult design trade-off. A system is desired in which a prefetch buffer system may support various software processes when the processes have various data usage rates.